What are Flip-Flops and Latches?
Latches and flip-flops are electronic circuits made from logic gates that have a memory effect. They can remember a single bit i.e. recall if it has previously been set to a 1 or a 0.
One type of latch is the SR latch. There is more than one way to make one, but one method is using two NOR logic gates. The circuit is as follows:
The SR latch has two inputs. The “S” input means set and the “R” input means reset, hence the SR name. The output, where the memorised bit appears, is labelled “Q”.
The SR latch also has a second output of Q with a bar over it, which is called the Q complement (also written Q’ as it’s easier to type on a keyboard). This means this output just does the opposite of whatever Q does. If Q is 1 then Q’ is 0 and vice versa.
The operation of an SR latch is as follows:
- Applying a 1 for any length of time to the R (reset) input causes the Q output to become zero and stick at zero. It doesn’t matter if R is now changed to 0 and back to 1 again, the Q output will stay at zero regardless. The Q’ output does the opposite and sticks at 1. The set input must be at zero in order to use reset.
- Applying a 1 for any length of time to the S (set) input causes the Q output to become 1 and stick at 1 even if the S input is subsequently changed. The Q’ does the opposite and will stick at zero. The reset input must be at zero in order to use the set input.
Hence the circuit effectively remembers which of S or R was activated last and records this with a 1 or 0 respectively at the output.
See this page to find out more about how an SR latch works in detail.
The truth table for an SR latch is as follows:
| S (set) | R (reset) | Q (output) | Q’ (output complement) |
|---|---|---|---|
| 0 | 0 | Last state (either 1 or 0) | Opposite of last state |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | Invalid | Invalid |
Notice this truth table is somewhat unusual. The output of Q when S and R are both zero depends on whatever we did last. If we have just previously applied a pulse to S, then Q is 1. If we have just previously applied a pulse to R then Q is 0. We can’t definitively write down in the truth table what it will be because we need to know what happened previously.
What about that slightly concerning last row where S and R are both 1? This state is called “invalid”. That is, Q and Q’ do not behave predictably and could end up being absolutely anything. Q’ could even end up being the same as Q which is contrary to the design. In this state the output of Q and Q’ are effectively random (or at least difficult to determine). What will happen depends on all kinds of factors including the relative quality of manufacturing of both of the NOR gates, the temperature and environment in which they are in. A random output state is not good and is a problem we might like to fix.
We can improve on the SR latch with a more sophisticated design called the JK latch to try and get rid of the uncertainty. The JK latch is as follows:
The JK latch works just like the SR latch. The set input is labelled J and the reset input is labelled K but the meaning and operation are exactly the same as S and R respectively in the previous design.
The AND gate between the reset (K) and Q means that the reset cannot be activated unless Q is outputting a 1. So the reset can only reset the latch back to zero in the case where the output is 1 i.e. you can only hit reset when the latch is already set. Similarly the AND gate between set (J) and Q’ means that the latch cannot be set unless it has been previously reset. The latch should only be set if the Q output is zero. The AND gate is connected to the complement (opposite) of Q, therefore the set can only be triggered if Q’ is 1.
When J and K are both set to one, the Q and Q’ outputs end up very rapidly oscillating back and forth (changing from 1 to 0 and back again) but are always the opposite of each other and are in a known state. This at least makes the output predictable, getting rid of that awkward invalid state where the outputs become random as in the SR latch. So this is a minor improvement, but there is still the oscillation problem to deal with. The JK latch though is more commonly used in the form of a flip-flop which addresses the issue.
Flip-flops are very similar to latches except they have an additional input called the clock. The clock is a digital signal that pulses with a precise regular heartbeat, just like the ticking of a clock. It is a stream of 1s with an even spacing.
Any change in the J and K inputs have no effect at all until such time as a pulse comes along on the clock input. Only when the clock pulse happens are any changes in the inputs respected. This is in contrast to latches where changes in the inputs change the state of the latch immediately.
Flip-flops are usually designed to only change state on one specific edge of the clock pulse. That is at the exact instant the pulse either arrives or at the exact point it disappears but not in between. The point at which the clock pulse changes from 0 to 1 is called the rising edge and the point where it goes from 1 to 0 is the falling edge.
The flip-flop may be configured either way round, either to work on the rising or falling edge of the clock but not both. A JK flip-flop that transitions on the edge of the clock, does not have a problem with oscillation. When J and K are both set to 1, the flip-flop will toggle, that is flip the output to the opposite state to whatever it is currently set to but then stick at that state.
A circuit for a JK flip-flop that works on a rising clock edge is as follows:
The two AND gates that activate J and K have been exchanged for 3-input versions. A clock signal is connected to each of the additional inputs. Now the J and K inputs do nothing unless the clock input also has a 1 on it (all three inputs of the AND gate must be 1 for it to output a 1). However, we want the flip-flop to only activate on the rising edge of a clock signal, when it changes from 0 to 1. So in front of this we have placed an additional circuit composed of a NOT gate and an AND gate. This is a rising edge detector.
The way this rising edge detector circuit works is it relies on the fact that real-world logic gates do not react instantly but take some time. When the clock pulse is at 0, the inverter outputs a 1. When the clock pulse changes from 0 to a 1 (a rising edge), for a tiny moment in time, there is a 1 at the top input to the AND gate but the inverter hasn’t yet caught up with the change and is still outputting a 1. The AND gate then gets a 1 on each input and outputs a 1 for a very short period of time. Very shortly afterwards, the inverter catches up and changes it’s output to a zero. The AND gate now outputs a zero. So the rising edge detector only outputs a 1 for the very short period of time when the clock signal is changing from 0 to 1.